A Router Architecture for Real - TimeCommunication in

| Parallel machines have the potential to satisfy the large computational demands of real-time applications. These applications require a predictable communication network, where time-constrained traac requires bounds on throughput and latency while good average performance suuces for best-eeort packets. This paper presents a new router architecture that tailors low-level routing, switching , arbitration, ow-control, and deadlock-avoidance policies to the connicting demands of each traac class. The router implements bandwidth regulation and deadline-based scheduling, with packet switching and table-driven multicast routing, to bound end-to-end delay and buuer requirements for time-constrained traac, while allowing best-eeort traf-c to capitalize on the low-latency routing and switching schemes common in modern parallel machines. To limit the cost of servicing time-constrained traac, the router includes a novel packet scheduler that shares link-scheduling logic across the multiple output ports, while masking the eeects of clock rollover on the represention of packet eligibility times and deadlines. Using the Verilog hardware description language and the Epoch silicon compiler, we demonstrate that the router design meets the performance goals of both traac classes in a single-chip solution. Verilog simulation experiments on a detailed timing model of the chip show how the implementation and performance properties of the packet scheduler scale over a range of architectural parameters.